Search - usb vhdl

[Technology Management] Altera_ByteBlaster_MV_II

Description: 基于FPGA USB下载线PCB图，直接可以拿过来用，程序网上一大把。-Based on FPGA USB download cable PCB maps can take up directly with, the program online a lot.
Platform: | Size: 566272 | Author: 李明 | Hits:

[USB develop] ISP1301[1]

Description: USB and OTG ISP1301 Spec. Thank!
Platform: | Size: 183296 | Author: Teo Hsieh | Hits:

[USB develop] cmos_fifo_usb

Description: cmos数据到fifo再到usb的fifo部分程序(68013a)-cmos data to fifo the fifo to the usb part of the procedures (68013a)
Platform: | Size: 158720 | Author: | Hits:

[MiddleWare] fpga_fifo_0122_02

Description: 可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序-To amend the agreement in the inside. Mainly cmos-fpga usb (68013a), except part of the procedure 68013a
Platform: | Size: 2322432 | Author: | Hits:

[VHDL-FPGA-Verilog] jtag_logic

Description: 这是自制altera usb_blaster所用到的CPLD程序，用VHDL语言写的。
Platform: | Size: 2048 | Author: wdy2004 | Hits:

[3G develop] usbhostslave

Description:
Platform: | Size: 701440 | Author: xiaojian | Hits:

[VHDL-FPGA-Verilog] ad_convert

Description: 用cpld控制时序通过usb传送数据到pc机的vhdl源码，用于一款心电图机。
Platform: | Size: 203776 | Author: 聂永波 | Hits:

[USB develop] usb_xilinx

Description:
Platform: | Size: 404480 | Author: hjj | Hits:

[VHDL-FPGA-Verilog] USB_jtag

Description: 用verilog编写的USB下载线程序实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.
Platform: | Size: 1571840 | Author: 霍飘摇 | Hits:

[VHDL-FPGA-Verilog] usb_jtag

Description: FPGA、CPLD芯片的usb数据下载线，下载速度是并口的5位，内有原理图用程序-FPGA, CPLD chip usb data download lines, download speed is the parallel port of the five, with a schematic diagram of procedures in
Platform: | Size: 234496 | Author: 李聚光 | Hits:

[VHDL-FPGA-Verilog] USBcomm

Description:
Platform: | Size: 10240 | Author: libing | Hits:

[Other] USB1_CORE

Description: USB v1.1 RTL and design specification
Platform: | Size: 312320 | Author: QiangWang | Hits:

[Other] 6805

Description: USB v1.1 RTL and design specification
Platform: | Size: 7168 | Author: QiangWang | Hits:

[VHDL-FPGA-Verilog] c8051

Description: USB v1.1 RTL and design specification
Platform: | Size: 1079296 | Author: QiangWang | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

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